emsys USB IP Cores

Overview

emsys Embedded Systems GmbH has long time experience with the development of reusable IP cores for USB.

All emsys USB IP cores are available at Fraunhofer CorePool for usage in ASIC designs. emsys USB IP for FPGA designs are distributed directly by emsys.

The following field-proven IP cores are available:

  • USB Function Core for Full- and Low-speed applications (FHG_USB_DEV)
  • USB Embedded Host Controller Core for Full- and Low-speed applications (FHG_USB_EHC)
  • USB Dual-Role Device Core for Full- and Low-speed applications (FHG_USB_OTGDRD)

Following USB 2.0 compliant Hi-Speed cores are also available:

  • USB Function Core for Hi-Speed and Full-speed applications (FHG_USB2_DEV)
  • Hi-Speed USB Embedded Host Controller Core (FHG_USB2_EHC)
  • Hi-Speed USB Embedded Dual-Role Device Core (FHG_USB2_OTGDRD)

Product Features

  • Compliant to the USB 2.0 Specification
  • Synthesizable, technology independent, fully synchronous design
  • FPGA and silicon proven
  • Verified with sophisticated test procedure to ensure high quality and proven technology deliverables
  • Hi-Speed capable USB cores provide a UTMI+ compliant interface according to specification
  • ULPI-ready
  • Handling of Session Request Protocol (SRP) according to the On-The-Go (OTG) Specification
  • Dual-role cores support the Host Negotiation Protocol (HNP)
  • Suspend/Resume/Remote Wakeup support
  • Large Buffer Management
    • Provided Buffer contains data/space for more than one transaction (transfer-based buffer management)
    • Hardware automatically performs data toggle and error handling
    • Optional Streaming Mode (automatic byte alignment)
  • Configurability
    • Scalable number of pipes (max. 15/31 data pipes, plus bi-directional pipe for Control Endpoint 0), data pipe direction configurable via software
    • Embedded Host cores have a scalable number of downstream ports (up to 15)
    • Scalable buffer memory size
    • Support of all transfer types (Control, Interrupt, Bulk and Isochronous)
    • 16/32 bit parallel generic microcontroller interface
    • Data interface via either dual-port memory, DMA master, or DMA slave interface
    • Various DMA interface adapters available (AHB, PCI, etc.)
    • All cores configurable to have an additional alternative buffer
  • FPGA evaluation platform available
emsys IP CoreUSB Speed GradeClockArea (gates)
FHG_USB_DEVFull-/Low-Speed12/48 MHz18 k
FHG_USB_EHCFull-/Low-Speed12/48 MHz22 k
FHG_USB_OTGDRDFull-/Low-Speed12/48 MHz24 k
FHG_USB2_DEVHi-Speed30/60 MHz28 k
FHG_USB2_EHCHi-Speed30/60 MHz38 k
FHG_USB2_OTGDRDHi-Speed30/60 MHz42 k

The actual area required for the IP cores depends on the configuration parameters.

The area listed for the Full- and Low-speed IP cores applies to a typical configuration with 2 pipes/endpoints and shows only the area of the core logic without the required RAM. Each additional pipe/endpoint requires about 3 k gates, each additional port about 1.5 k gates.

The area listed for the Hi-Speed IP core applies to a typical configuration with 2 pipes/endpoints. Each additional pipe/endpoint requires about 4 k gates, each additional port about 2 k gates. All Hi-Speed cores have an 8/16 bit UTMI+ compliant interface.

Architecture

emsys USB IP cores were designed to fit all customer environments. Therefore, great importance was attached to the interface design.

In principle, each USB core provides three interfaces:

  • USB Interface
    • Full-speed cores provide a serial interface for connection to any external Full-speed transceiver or a USB I/O cell on the customer's target technology
    • Hi-Speed cores provide a UTMI+ compliant interface for connection to UTMI/UTMI+ compliant external transceivers or a UTMI macrocell for the customer's target technology
  • Register Interface
    Generic asynchronous register interface allows connecting any controller or backbone bus.
  • Data Interface
    All cores can be configured to exchange data using an external dual-port memory or DMA. DMA capability requires a small external memory for buffering data.

Deliverables

emsys USB IP Cores can be ordered as:

  • VHDL Source code for ASIC designs
  • Synopsys Design Ware component for ASIC designs
  • VHDL/Verilog netlist for FPGA designs (Xilinx, Actel, Altera)

The complete design kit contains the following parts:

  • The IP component, depending on the selected license
  • VHDL pre-compiled simulation models if no VHDL Source code license was selected
  • VHDL/Verilog test suite with reference testbench
  • IP integration guideline
  • Synthesis scripts
  • Optional: PCI evaluation board