emsys IEEE 1394 IP Cores

Overview

emsys Embedded Systems GmbH has long time experience with development of reusable IP cores for IEEE 1394 (FireWire™).

The following field-proven IP cores are available:

  • IEEE 1394a Link Layer Core (FHG_1394A_LINK), allowing data rates up to 400 Mbit/s
  • IEEE 1394b Link Layer Core (FHG_1394B_LINK), allowing data rates up to 800 Mbit/s

Product Features

  • Synthesizable, technology independent, fully synchronous design
  • Fully compliant to IEEE 1394-1995 Specification
  • FHG_1394A_LINK fully compliant to IEEE 1394a Specification
  • FHG_1394B_LINK fully compliant to IEEE 1394b Specification
  • Generic 8/16/32 bit microcontroller interface
  • Supports 100, 200, 400, and 800 Mbit/s transfer rates
  • Provides full link layer and several transaction layer functions
  • Supports asynchronous transmission and reception (maximum packet size: 4096 bytes)
  • Supports isochronous transmission through separate hardware channel (maximum packet size: 8192 bytes)
  • Supports simple hardware interface for isochronous transmission
  • Performs 32 bit CRC generation and check
  • Automatic retry for asynchronous data packets
  • AMBA AHB ready (AHB slave interface configuration) interface or AHB slave interface with dual-port RAM for payload data)
  • AHB interface tested with Synopsys AMBA Verification Suite
  • Dual-port RAM interface available with scalable memory size
  • PCI evaluation platform available
  • Generic IEEE 1394 Software Library available

Technology Requirements

The emsys IEEE 1394 IP Cores can be used in ASIC and FPGA designs. Despite the high PHY clock rate required for the FHG_1394B_LINK, this core can also be implemented using current FPGA technologies.

The FHG_1394B_LINK has successfully been implemented in various projects with different FPGA technologies (Xilinx Virtex2 and Spartan3, Altera CycloneII).

emsys IP CoreClockArea (gates)
FHG_1394A_LINK49.152 MHz25 k
FHG_1394B_LINK98.304 MHz26 k

The actual area required for the IP cores depends on the configuration parameters. The area listed above applies to a typical configuration and shows only the area of the core logic without the required RAM.

Architecture

emsys IEEE 1394 IP Cores have been designed to fit every customer environment. Therefore, great importance was attached to the interface design.

In principle, the IEEE 1394 core provides three interfaces:

  • Phy Interface
    Interface compliant to 1394a (for FHG_1394A_LINK) or 1394b (for FHG_1394B_LINK) physical layer.
  • Register Interface
    Generic asynchronous register interface allows connecting any controller or backbone bus.
  • Data Interface
    Both IEEE 1394 cores provide a high bandwidth interface for streaming data. This interface supports isochronous transmission without automatic header insertion.

Deliverables

The emsys IEEE 1394 IP Cores can be ordered as:

  • VHDL Source code for ASIC designs
  • Synopsys Design Ware component for ASIC designs
  • VHDL/Verilog netlist for FPGA designs (Xilinx, Actel, Altera)
The complete design kit consists of the following parts:
  • IP component (depending on the selected license)
  • VHDL pre-compiled simulation models (if no VHDL source code license was selected)
  • VHDL/Verilog test suite with reference testbench
  • IP integration guideline
  • Synthesis scripts
  • Optional: PCI evaluation board

For ASIC designs, the core is available from Fraunhofer IIS. For FPGA designs, please contact the emsys Sales Department.