emsys Gigabit Ethernet IP Core

Overview

emsys Embedded Systems GmbH has long time experience with development of reusable hardware IP.

The emsys Gigabit Ethernet core is a scalable, high performance IP module for usage in ASIC and FPGA designs to integrate an IEEE 802.3 Gigabit Ethernet Controller into embedded systems. It provides an easy to use programming interface for interconnecting almost any 8/16/32 bit microcontroller or DSP and is optimized for camera/visual applications.

Product Features

  • Synthesizable, technology independent, fully synchronous design
  • Fully compliant to IEEE 802.3-2000 Specification
  • Generic 8/16/32 bit microcontroller interface
  • Supports a GMII interface to the Gigabit Ethernet Phy
  • Supports 10, 100, and 1000 Mbit/s transfer rates in full or half duplex mode
  • Provides full Ethernet Controller functionality (OSI Layers 1 and 2)
  • Rx/Tx FIFO for non-highspeed data (asynchronous transmission and reception) with scalable FIFO sizes
  • Rx FIFO can hold multiple packets
  • Highspeed transmission by separate hardware channel (high bandwidth data channel)
  • Supports simple hardware interface for high bandwidth data channel
  • Supports hardware generated UDP packets for high bandwidth data channel (configurable via registers)
  • Performs hardware CRC generation and check
  • PCI evaluation module available

Technology Requirements

The emsys Gigabit Ethernet IP core can be used in ASIC and FPGA designs. Despite the high Phy clock rate required, this core can also be implemented using current FPGA technologies. The core has successfully been implemented in a Xilinx Virtex2 device.

emsys IP CoreClockArea (gates)
FHG_GIGABIT_LINK100 MHz36 k

The actual area required for the IP core depends on the configuration parameters. The area listed above applies to a typical configuration and shows only the area of the core logic without the required RAM.

Architecture

The emsys Gigabit Ethernet IP core was designed to fit in every customer environment. Therefore, great importance was attached to the design of the interface.

In principle, the emsys Gigabit Ethernet IP core provides four interfaces:

  • High Bandwidth Interface
    Special data interface for streaming data (Tx). This interface supports direct transmission of data with automatic header insertion.
  • Register Interface
    Generic asynchronous register interface allows connecting any controller or backbone bus.
  • Data Interface
    The data exchange is performed using dual-port memory.
  • MAC Interface

High Bandwidth Data Interface

The High Bandwidth Data Interface receives streaming data. This data will be sent to the data Tx controller, which is responsible for automatic MAC, IP, and UDP header insertion.

The header information is stored in registers. The MAC Controller creates a preamble, start-of-frame delimiter, and a frame check sequence.

Deliverables

The emsys Gigabit Ethernet IP core can be ordered as:

  • VHDL Source code for ASIC designs
  • Synopsys Design Ware component for ASIC designs
  • VHDL/Verilog netlist for FPGA designs (Xilinx, Actel, Altera)

The complete design kit contains the following parts:

  • IP component (depending on the selected license)
  • VHDL pre-compiled simulation models (if no VHDL source code license was selected)
  • VHDL/Verilog test suite with reference testbench
  • IP integration guideline
  • Synthesis scripts
  • Optional: PCI evaluation board

For ASIC designs, the core is available from Fraunhofer IIS. For FPGA designs, please contact the emsys Sales Department.