USB Cores

Portfolio

The following USB cores are available: 

• USB Function IP Core for full-/low-speed applications (FHG_USB_DEV)
• USB Host Controller IP Core for full-/low-speed applications (FHG_USB_EHC)
• USB OTG-Dual-Role Host/Device Core for full-/low-speed applications (FHG_USB_OTGDRD)
• USB Function IP Core for high-/full-speed applications (FHG_USB2_DEV)
• USB Function IP Core for high-/full-speed vision applications (FHG_USB2_DEV_VISION)
• USB Host Controller IP Core for high-/full-/low-speed applications (FHG_USB2_EHC)
• USB OTG-Dual-Role Host/Device IP Core for high-/full-/low-speed applications (FHG_USB2_OTGDRD)

All emsys USB IP cores are available at Fraunhofer CorePool for the usage in ASIC designs, whereas emsys USB IP for FPGA design are directly available at emsys. Altera FPGA customers may obtain IP through IFI.

Features

All USB Cores provide the following features:

• Compliant to the USB 2.0 Specification
• Synthesizable, technology independent, fully synchronous design
• FPGA and silicon proven
• Verified with sophisticated test procedure to ensure high quality and proven technology deliverables
• High-speed capable USB cores have an UTMI+ compliant interface according the UTMI+ Specification
• ULPI compliant interface
  
• Handling of Session Request Protocol (SRP) as described in the On-The-Go (OTG) Specification
• Dual-role cores support the Host Negotiation Protocol (HNP)
• Suspend/Resume/Remote Wakeup support
• Provided buffer contains data/space for more than one transaction (transfer-based buffer management)
• Hardware does automatically perform data toggle handling/error handling
• Streaming mode (automatic byte alignment) can be activated
• Configurability
• Scalable number of pipes (max 15/31 data pipes + bi-directional pipe for Control Endpoint 0), data pipes can be configured by software for IN or OUT direction
• Embedded host cores can have a scalable number of downstream ports (1..15)
• Scalable buffer size
• Support of all transfer types (Control, Interrupt, Bulk and Isochronous transfer)
• 16/32 bit parallel generic microcontroller interface
• Data interface either via Dual Port Memory or DMA master or DMA slave interface
• Various DMA interface adapters are available (AHB, PCI etc.)
• All cores can be configured to have an additional alternative buffer
• FPGA evaluation platform available

Architecture

USB IP Core architecture

emsys USB IP cores are designed to fit all customer environments. Therefore, there has been attached a great importance to the design of the interface. In principle, every USB core provides three interfaces:

USB Interface

• Full-speed cores have a serial interface for connection to every external full-speed transceiver or a USB I/O cell on the custumers target technology
• High-speed cores have an UTMI+ and ULPI compliant interface that allows the connection to  external transceivers, or an UTMI macrocell for the customer's target technology

Register Interface

• Generic asynchronous register interface which allows the connection of every controller or backbone bus

Data Interface

• All cores can be configured to exchange data by using an external dual-port memory, or by DMA. DMA capability requires a small external memory for buffering data