Gigabit Ethernet Core
IEEE 802.3 Gigabit Ethernet IP Core for Vision Applications
The Gigabit Ethernet core (EMSYS_GIGABIT_LINK) is a scalable, high performance IP module for usage in ASIC and FPGA designs to integrate an IEEE 802.3 Gigabit Ethernet Controller to an embedded system. It provides an easy to use programming interface for the usage of almost every microcontroller or DSP. The IP Core is optimized for camera/vision applications.
The Gigabit Ethernet core is available at Fraunhofer CorePool for the usage in ASIC designs, whereas emsys Ethernet IP for FPGA design are directly available from emsys.
- Fully compliant to IEEE 802.3-2002 Specification
- Generic 8/16/32 bit microcontroller interface
- Supports a GMII interface to the gigabit ethernet PHY
- Support of 10, 100 and 1000 Mbit/s transfer rates in half or full duplex mode
- Provides full Ethernet Controller functionality (OSI Layer 1 and 2)
- RX/TX FIFO buffer for non high speed data (asynchronous transmit and receive) with scalable FIFO sizes
- RX FIFO buffer can hold multiple packets
- High speed transmit by separate hardware channel (high bandwidth data channel)
- Supports simple hardware interface for high bandwidth data channel
- Supports UDP hardware generated packets for high bandwidth data channel, easy to configure via configuration registers
- Performs hardware CRC generation and verification
- Technology independent, fully synchronous RTL implementation
- PCI evaluation module available
- Linux TCP/IP stack available
The Gigabit Ethernet core is optimized for vision applications. The asynchronous transmit and receive interface is optimized for area, but supports all necessary ethernet controller functionality.
Additionally, the Gigabit Ethernet core supports high speed transmit through its high-bandwidth interface. This external interface is optimized for speed and bandwidth. This interface supports hardware generated UDP packets. So the Gigabit Ethernet core is ideal for audio as well as video streaming applications.